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74AHC2G00; 74AHCT2G00
Dual 2-input NAND gate
Rev. 02 -- 12 January 2009 Product data sheet
1. General description
The 74AHC2G00; 74AHCT2G00 is a high-speed Si-gate CMOS device. The 74AHC2G00; 74AHCT2G00 provides two 2-input NAND gates.
2. Features
I Symmetrical output impedance I High noise immunity I ESD protection: N HBM JESD22-A114E exceeds 2000 V N MM JESD22-A115-A exceeds 200 V N CDM JESD22-C101C exceeds 1000 V I Low power dissipation I Balanced propagation delays I Multiple package options I Specified from -40 C to +85 C and from -40 C to +125 C
3. Ordering information
Table 1. Ordering information Package Temperature range Name 74AHC2G00DP 74AHCT2G00DP 74AHC2G00DC 74AHCT2G00DC 74AHC2G00GD 74AHCT2G00GD -40 C to +125 C XSON8U -40 C to +125 C VSSOP8 -40 C to +125 C TSSOP8 Description Version plastic thin shrink small outline package; 8 leads; body SOT505-2 width 3 mm; lead length 0.5 mm plastic very thin shrink small outline package; 8 leads; SOT765-1 body width 2.3 mm plastic extremely thin small outline package; no leads; SOT996-2 8 terminals; UTLP based; body 3 x 2 x 0.5 mm Type number
NXP Semiconductors
74AHC2G00; 74AHCT2G00
Dual 2-input NAND gate
4. Marking
Table 2. Marking Marking code A00 C00 A00 C00 A00 C00 Type number 74AHC2G00DP 74AHCT2G00DP 74AHC2G00DC 74AHCT2G00DC 74AHC2G00GD 74AHCT2G00GD
5. Functional diagram
&
1A 1B 2A 2B 1Y
2Y
&
001aah748
001aah749
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
B Y A
mna099
Fig 3.
Logic diagram (one gate)
74AHC_AHCT2G00_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 12 January 2009
2 of 14
NXP Semiconductors
74AHC2G00; 74AHCT2G00
Dual 2-input NAND gate
6. Pinning information
6.1 Pinning
74AHC2G00 74AHCT2G00 74AHC2G00 74AHCT2G00
1A 1B 2Y GND 1 2 3 4
001aaj388
1A 1B 8 7 6 5 VCC 1Y 2B 2A GND 2Y
1 2 3 4
8 7 6 5
VCC 1Y 2B 2A
001aaj387
Transparent top view
Fig 4.
Pin configuration SOT505-2 (TSSOP8) and SOT765-1 (VSSOP8)
Fig 5.
Pin configuration SOT996-2 (XSON8U)
6.2 Pin description
Table 3. Symbol 1A, 2A 1B, 2B GND 1Y, 2Y VCC Pin description Pin 1, 5 2, 6 4 7, 3 8 Description data input data input ground (0 V) data output supply voltage
7. Functional description
Table 4. Input nA L L H H
[1]
Function table[1] Output nB L H L H nY H H H L
H = HIGH voltage level; L = LOW voltage level.
74AHC_AHCT2G00_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 12 January 2009
3 of 14
NXP Semiconductors
74AHC2G00; 74AHCT2G00
Dual 2-input NAND gate
8. Limiting values
Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC VI IIK IOK IO ICC IGND Tstg Ptot
[1] [2]
Parameter supply voltage input voltage input clamping current output clamping current output current supply current ground current storage temperature total power dissipation
Conditions
Min -0.5 -0.5
Max +7.0 +7.0 20 25 75 +150 250
Unit V V mA mA mA mA mA C mW
VI < -0.5 V VO < -0.5 V or VO > VCC + 0.5 V -0.5 V < VO < VCC + 0.5 V
[1] [1]
-20 -75 -65
Tamb = -40 C to +125 C
[2]
-
The input and output voltage ratings may be exceeded if the input and output current ratings are observed. For TSSOP8 package: above 55 C the value of Ptot derates linearly with 2.5 mW/K. For VSSOP8 package: above 110 C the value of Ptot derates linearly with 8 mW/K. For XSON8U package: above 45 C the value of Ptot derates linearly with 2.4 mW/K.
9. Recommended operating conditions
Table 6. Recommended operating conditions Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC VI VO Tamb t/V supply voltage input voltage output voltage ambient temperature input transition rise and fall rate VCC = 3.3 V 0.3 V VCC = 5.0 V 0.5 V Conditions Min 2.0 0 0 -40 74AHC2G00 Typ 5.0 +25 Max 5.5 5.5 VCC +125 100 20 4.5 0 0 -40 74AHCT2G00 Min Typ 5.0 +25 Max 5.5 5.5 VCC +125 20 V V V C ns/V ns/V Unit
10. Static characteristics
Table 7. Static characteristics Voltages are referenced to GND (ground = 0 V). Symbol Parameter 74AHC2G00 VIH HIGH-level input voltage VCC = 2.0 V VCC = 3.0 V VCC = 5.5 V 1.5 2.1 3.85 1.5 2.1 3.85 1.5 2.1 3.85 V V V Conditions Min 25 C Typ Max -40 C to +85 C -40 C to +125 C Unit Min Max Min Max
74AHC_AHCT2G00_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 12 January 2009
4 of 14
NXP Semiconductors
74AHC2G00; 74AHCT2G00
Dual 2-input NAND gate
Table 7. Static characteristics ...continued Voltages are referenced to GND (ground = 0 V). Symbol Parameter VIL LOW-level input voltage Conditions Min VCC = 2.0 V VCC = 3.0 V VCC = 5.5 V VOH HIGH-level VI = VIH or VIL output voltage IO = -50 A; VCC = 2.0 V IO = -50 A; VCC = 3.0 V IO = -50 A; VCC = 4.5 V IO = -4.0 mA; VCC = 3.0 V IO = -8.0 mA; VCC = 4.5 V VOL LOW-level VI = VIH or VIL output voltage IO = 50 A; VCC = 2.0 V IO = 50 A; VCC = 3.0 V IO = 50 A; VCC = 4.5 V IO = 4.0 mA; VCC = 3.0 V IO = 8.0 mA; VCC = 4.5 V II ICC CI input leakage current VI = 5.5 V or GND; VCC = 0 V to 5.5 V 1.9 2.9 4.4 2.58 3.94 25 C Typ 2.0 3.0 4.5 0 0 0 1.5 Max 0.5 0.9 1.65 0.1 0.1 0.1 0.36 0.36 0.1 10 10 -40 C to +85 C -40 C to +125 C Unit Min 1.9 2.9 4.4 2.48 3.8 Max 0.5 0.9 1.65 0.1 0.1 0.1 0.44 0.44 1.0 10 10 Min 1.9 2.9 4.4 2.40 3.70 Max 0.5 0.9 1.65 0.1 0.1 0.1 0.55 0.55 2.0 40 10 V V V V V V V V V V V V V A A pF
supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V input capacitance HIGH-level input voltage LOW-level input voltage VCC = 4.5 V to 5.5 V VCC = 4.5 V to 5.5 V
74AHCT2G00 VIH VIL VOH 2.0 0.8 2.0 0.8 2.0 0.8 V V
HIGH-level VI = VIH or VIL; VCC = 4.5 V output voltage IO = -50 A IO = -8.0 mA LOW-level VI = VIH or VIL; VCC = 4.5 V output voltage IO = 50 A IO = 8.0 mA input leakage current VI = 5.5 V or GND; VCC = 0 V to 5.5 V
4.4 3.94 -
4.5 0 -
0.1 0.36 0.1 1.0 1.35
4.4 3.8 -
0.1 0.44 1.0 10 1.5
4.4 3.70 -
0.1 0.55 2.0 40 1.5
V V V V A A mA
VOL
II ICC ICC
supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V additional per input pin; VI = 3.4 V; supply current other inputs at VCC or GND; IO = 0 A; VCC = 5.5 V input capacitance
CI
-
1.5
10
-
10
-
10
pF
74AHC_AHCT2G00_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 12 January 2009
5 of 14
NXP Semiconductors
74AHC2G00; 74AHCT2G00
Dual 2-input NAND gate
11. Dynamic characteristics
Table 8. Dynamic characteristics GND = 0 V; for test circuit see Figure 7. Symbol Parameter 74AHC2G00 tpd propagation delay nA, nB to nY; see Figure 6 VCC = 3.0 V to 3.6 V CL = 15 pF CL = 50 pF VCC = 4.5 V to 5.5 V CL = 15 pF CL = 50 pF CPD power per buffer; dissipation CL = 50 pF; fi = 1 MHz; capacitance VI = GND to VCC propagation delay nA, nB to nY; see Figure 6 VCC = 4.5 V to 5.5 V CL = 15 pF CL = 50 pF CPD power per buffer; dissipation CL = 50 pF; fi = 1 MHz; capacitance VI = GND to VCC
tpd is the same as tPLH and tPHL. Typical values are measured at VCC = 3.3 V. Typical values are measured at VCC = 5.0 V. CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD x VCC2 x fi x N + (CL x VCC2 x fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; (CL x VCC2 x fo) = sum of the outputs.
[4] [4] [3] [1] [2]
Conditions Min
25 C Typ Max
-40 C to +85 C -40 C to +125 C Unit Min Max Min Max
-
4.5 6.5 3.5 4.9 17
7.9 11.4 5.5 7.5 -
1.0 1.0 1.0 1.0 -
9.5 13.0 6.5 8.5 -
1.0 1.0 1.0 1.0 -
10.5 14.5 7.0 9.5 -
ns ns ns ns pF
74AHCT2G00 tpd
[1] [3]
1.0 1.0 -
3.6 5.0 18
6.2 7.9 -
1.0 1.0 -
7.1 9.0 -
1.0 1.0 -
8.0 10.0 -
ns ns pF
[1] [2] [3] [4]
74AHC_AHCT2G00_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 12 January 2009
6 of 14
NXP Semiconductors
74AHC2G00; 74AHCT2G00
Dual 2-input NAND gate
12. Waveforms
VI nA, nB input GND t PHL VOH nY output VOL VM
001aae972
VM
t PLH
Measurement points are given in Table 9. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 6. Table 9. Type
The input (nA and nB) to output (nY) propagation delays. Measurement points Input VM 0.5VCC 1.5 V Output VM 0.5VCC 0.5VCC
74AHC2G00 74AHCT2G00
74AHC_AHCT2G00_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 12 January 2009
7 of 14
NXP Semiconductors
74AHC2G00; 74AHCT2G00
Dual 2-input NAND gate
VI negative pulse 0V
tW 90 % VM 10 % tf tr tr tf 90 % VM 10 % tW VM VM
VI positive pulse 0V
VCC
VCC
G
VI
VO
RL
S1
DUT
RT CL
open
001aad983
Test data is given in Table 10. Definitions test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including jig and probe capacitance. RL = Load resistance. S1 = Test selection switch.
Fig 7. Table 10. Type
Test circuit for measuring switching times Test data Input VI tr, tf 3 ns 3 ns VCC 3V Load CL 15 pF, 50 pF 15 pF, 50 pF RL 1 k 1 k S1 position tPHL, tPLH open open
74AHC2G00 74AHCT2G00
74AHC_AHCT2G00_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 12 January 2009
8 of 14
NXP Semiconductors
74AHC2G00; 74AHCT2G00
Dual 2-input NAND gate
13. Package outline
TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm SOT505-2
D
E
A
X
c y HE vMA
Z
8
5
A pin 1 index
A2 A1
(A3)
Lp L
1
e bp
4
wM
detail X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.00 A2 0.95 0.75 A3 0.25 bp 0.38 0.22 c 0.18 0.08 D(1) 3.1 2.9 E(1) 3.1 2.9 e 0.65 HE 4.1 3.9 L 0.5 Lp 0.47 0.33 v 0.2 w 0.13 y 0.1 Z(1) 0.70 0.35 8 0
Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT505-2 REFERENCES IEC JEDEC --JEITA EUROPEAN PROJECTION ISSUE DATE 02-01-16
Fig 8.
Package outline SOT505-2 (TSSOP8)
(c) NXP B.V. 2009. All rights reserved.
74AHC_AHCT2G00_2
Product data sheet
Rev. 02 -- 12 January 2009
9 of 14
NXP Semiconductors
74AHC2G00; 74AHCT2G00
Dual 2-input NAND gate
VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm
SOT765-1
D
E
A X
c y HE vMA
Z
8
5
Q A pin 1 index A2 A1 (A3) Lp L
1
e bp
4
wM
detail X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1 A1 0.15 0.00 A2 0.85 0.60 A3 0.12 bp 0.27 0.17 c 0.23 0.08 D(1) 2.1 1.9 E(2) 2.4 2.2 e 0.5 HE 3.2 3.0 L 0.4 Lp 0.40 0.15 Q 0.21 0.19 v 0.2 w 0.13 y 0.1 Z(1) 0.4 0.1 8 0
Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT765-1 REFERENCES IEC JEDEC MO-187 JEITA EUROPEAN PROJECTION
ISSUE DATE 02-06-07
Fig 9.
Package outline SOT765-1 (VSSOP8)
(c) NXP B.V. 2009. All rights reserved.
74AHC_AHCT2G00_2
Product data sheet
Rev. 02 -- 12 January 2009
10 of 14
NXP Semiconductors
74AHC2G00; 74AHCT2G00
Dual 2-input NAND gate
XSON8U: plastic extremely thin small outline package; no leads; 8 terminals; UTLP based; body 3 x 2 x 0.5 mm
SOT996-2
D
B
A
E
A
A1
detail X terminal 1 index area e1 L1
1
e
b
4
v w
M M
CAB C
C y1 C y
L2
L
8 5
X
0
1 scale
2 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max 0.5 A1 0.05 0.00 b 0.35 0.15 D 2.1 1.9 E 3.1 2.9 e 0.5 e1 1.5 L 0.5 0.3 L1 0.15 0.05 L2 0.6 0.4 v 0.1 w 0.05 y 0.05 y1 0.1
OUTLINE VERSION SOT996-2
REFERENCES IEC --JEDEC JEITA ---
EUROPEAN PROJECTION
ISSUE DATE 07-12-18 07-12-21
Fig 10. Package outline SOT996-2 (XSON8U)
74AHC_AHCT2G00_2 (c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 12 January 2009
11 of 14
NXP Semiconductors
74AHC2G00; 74AHCT2G00
Dual 2-input NAND gate
14. Abbreviations
Table 11. Acronym CDM DUT ESD HBM MM Abbreviations Description Charged Device Model Device Under Test ElectroStatic Discharge Human Body Model Machine Model
15. Revision history
Table 12. Revision history Release date 20090112 Data sheet status Product data sheet Change notice Supersedes 74AHC_AHCT2G00_1 Document ID 74AHC_AHCT2G00_2 Modifications:
* * *
The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Added type number 74AHC2G00GD and 74AHCT2G00GD (XSON8U package). Product specification -
74AHC_AHCT2G00_1
20040101
74AHC_AHCT2G00_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 12 January 2009
12 of 14
NXP Semiconductors
74AHC2G00; 74AHCT2G00
Dual 2-input NAND gate
16. Legal information
16.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.
16.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
17. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
74AHC_AHCT2G00_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 12 January 2009
13 of 14
NXP Semiconductors
74AHC2G00; 74AHCT2G00
Dual 2-input NAND gate
18. Contents
1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4 Dynamic characteristics . . . . . . . . . . . . . . . . . . 6 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 12 Legal information. . . . . . . . . . . . . . . . . . . . . . . 13 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 13 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Contact information. . . . . . . . . . . . . . . . . . . . . 13 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 12 January 2009 Document identifier: 74AHC_AHCT2G00_2

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